A liquid crystal display panel may generally include an array substrate, a color filter substrate and a gate driving circuit. The gate driving circuit supplies scanning signals to thin film transistors on the array substrate. To enhance integration of the display panel, the gate driving circuit may be integrated into the array substrate.
The gate driving circuit 1 integrated into the array substrate comprises a plurality of thin film transistors and connection gate lines each of which is connected between two adjacent thin film transistors, as shown in FIG. 1 (FIG. 1 shows thin film transistors T1, T2, T3 and T4 in the gate driving circuit), FIG. 2 shows the connection relationship between two adjacent thin film transistors, and as shown in the FIG. 2, a connection gate line 12 is connected between two adjacent thin film transistors 10.
FIG. 3 shows a flowchart of a method for forming a pattern of the active layer of the thin film transistor in the gate driving circuit and forming a pattern of a source and a drain of the thin film transistor in the gate driving circuit when an array substrate is manufactured in the prior art. After gates 11, a connection gate line 12, a gate insulation layer 20 and a semiconductor layer 30 of the thin film transistors are formed, the method for manufacturing the array substrate further comprises steps of: forming a photoresist layer 40 (FIG. 3a)→performing an exposure and a development (FIG. 3a)→etching the semiconductor layer, so that the active layers of two adjacent thin film transistors are separated from each other; then etching the gate insulation layer (3c)→ashing the photoresist layer above the remaining semiconductor layer (3d)→etching so as to form an active layer 31, and peeling off the remaining photoresist (3e)→forming a source and drain metal layer 50, and then forming a photoresist layer thereon; performing an exposure and a development (3f)→etching so as to form the sources 51 and drains 52, and peeling off the remaining photoresist (3g).
It can be seen from FIG. 3a, the part of the photoresist layer above the connection gate line 12 is thinner than the remaining photoresist layer. Thus, in the FIG. 3b, after exposure, there is no photoresist layer remaining above the connection gate line 12. Therefore, as shown in FIG. 3g, when the source and drain metal layer is etched using etchant to form the source and the drain, the connection gate line is likely to be etched away.
Therefore, how to protect the connection gate line connected between two adjacent thin film transistors from being damaged when the source and drain metal layer is etched has been a technical problem to be solved.